Highly sophisticated receiver techniques for accurately recovering digital data from a serial transmitted binary modulated waveform have been previously developed. As the frequency i.e., bit rate, of the data has increased, the noise sources such as timing jitter, caused by transmission medium and asymmetrical rise and fall times of the components in the transmitter/receiver and in the interconnecting link, and other sources make increasingly more stringent demands on the data recovery circuits. Most commonly, in the prior art, the receiver employs a circuit for recovering the bit clock rate from the transmitted incoming serial data and then locks a voltage controlled oscillator (VCO) to a frequency derived from the bit clock rate of the incoming serial data. Usually, this employs a so called Phase Locked Loop (PLL) which tracks the error in phase or frequency between the VCO and the incoming data, employing averaging and smoothing, and applies this smoothed error signal to correct the VCO. The receiver circuit then employs the PLL recovered bit clock which controls the receiver timing and in particular controls the time that the incoming serial data is sampled. This sampling moment is known as the "center of the data eye." Due to noise sources of jitter and asymmetry, it is understood that the state of a binary signal is most uncertain in the vicinity of the transitions from one level to the other. Accordingly, even in the presence of such noise sources, the center region of the data eye is the region in the waveform when the data is most likely to be correctly and reliability read.
In the prior art, even a slight frequency difference between the data rate and the VCO generated bit clock, was integrated and resulted in large phase error so that the sampling no longer takes place at the center of the eye. In conventional CMOS, the PLL performance is generally good at frequencies under 125 Mb/s. Another problem with the prior art PLL is that PLLs generally are implemented in analogue circuitry with capacitors and other lumped parameters which are difficult or impossible to implement in an large scale integrated circuit. Large scale integrated circuit process technology lends itself more readily to digital implementation as opposed to analogue linear circuits.
Digital phased locked loops are known, such as is found in U.S. Pat. No. 4,584,695 and U.S. Pat. No. 4,821,297. These prior patented techniques have used delay lines to produce a plurality of multiphase clock pulses, and then attempt to select the clock pulse with the appropriate phase to read the data. Such techniques need either analogue controls, or a fixed clock running at the bit rate, or special data coding schemes such as the Manchester encoding.
A need exists for an all digital data recovery solution which performs high speed data recovery functions without requiring recovery of a bit rate clock or use of a PLL.